スポンサーリンク
Kobe Univ. Kobe‐shi Jpn | 論文
- An Error-Correcting Version of the Leiss's Parser for Context-Free Languages
- Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_/V_ and Micro-V_-Hopping (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation
- Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements(Analog Circuits and Related SoC Integration Technologies)
- A-1-3 極低消費電力バンドギャップリファレンス回路の高精度化(A-1.回路とシステム,一般セッション)
- An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs(Novel Device Architectures and System Integration Technologies)
- C-12-63 ナノアンペア電流源回路の電流バラツキ補正(C-12.集積回路,一般セッション)
- Trends of On-Chip Interconnects in Deep Sub-Micron VLSI (Interconnect Technique, VLSI Design Technology in the Sub-100nm Era)
- A-1-2 サブスレッショルドLSIに適したオンチップ電源回路の検討(A-1.回路とシステム,一般セッション)
- Optimization of selection and mating schemes in closed broiler lines
- Comparison of Selection Schemes for Achieving Desired Genetic Gains in Closed Broiler Lines
- Estimation of Genetic Parameters and Trends for Additive Direct and Maternal Genetic Effects for Birth and Calf-market Weights in Japanese Black Beef Cattle
- Estimation of Genetic Parameters and Trends for Additive Direct and Maternal Genetic Effects for Birth and Calf-market Weights in Japanese Black Beef Cattle
- Current Situation and Problems of Japanese Beef Cattle Breeding (SAFEA21 THIRD KOBE SYMPOSIUM ON AGRICULTURE, FOOD AND ENVIRONMENT IN ASIA : TOWARDS THE 21ST CETURY)
- Prediction of Response and Inbreeding under Selection Based on Best Linear Unbiased Prediction in Closed Broiler Lines
- Property of Difference between Two Predicted Breeding Values from BLUP Methodology
- Prediction of Response and Inbreeding under Selection Based on Best Linear Unbiased Prediction in Closed Broiler Lines
- Property of Difference between Two Predicted Breeding Values from BLUP Methodology
- C-12-34 超低電力CMOSスマート温度センサ回路(C-12.集積回路,一般セッション)
- A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond