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Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University | 論文
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
- Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
- Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)
- Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors
- Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using V_T-Control Doping Region
- Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits