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IMEC, Kapeldreef 75, B-3001 Leuven, Belgium | 論文
- Charge Trapping in SiOx/ZrO2 and SiOx/TiO2 Gate Dielectric Stacks
- The Effect of Backside Particles on Substrate Topography
- W versus Co--Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes
- Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology
- Wafer-Level Electrical Evaluation of Vertical Carbon Nanotube Bundles as a Function of Growth Temperature
- Si
- Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications
- Deep Levels in High-Temperature 1 MeV Electron-Irradiated n-Type Czochralski Silicon
- Mask Effects on Resist Variability in Extreme Ultraviolet Lithography
- Mask Effects on Resist Variability in Extreme Ultraviolet Lithography (Special Issue : Microprocesses and Nanotechnology)
- Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme