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Graduate School of Information Science Tohoku University | 論文
- Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling
- Capacity Design of Guaranteed-QoS VPN
- Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification(Novel Device Architectures and System Integration Technologies)
- Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, VLSI Design and CAD Algorithms)
- C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages
- Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture(New System Paradigms for Integrated Electronics)
- Architecture of a high-performance stereo vision VLSI processor
- A VLSI-Oriented Model-Based Robot Vision Processor for 3-D Instrumentation and Object Recognition (Special Issue on Super Chip for Intelligent Integrated Systems)
- Generalized Hough Transform VLSI Processor for Model-Based Edge Detection
- Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation
- Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
- Memory Allocation for Multi-Resolution Image Processing
- Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
- Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs (Special Issue on Super Chip for Intelligent Integrated Systems)
- Special Section on VLSI Technology toward Frontiers of New Market
- A Minimum-Latency Linear Array FFT Processor for Robotics
- Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size
- Multiple-Valued Code Assignment Algorithm for VLSI-Oriented Highly Parallel K-Ary Operation Circuits (Special Issue on New Architecture LSIs)
- Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model
- Design of a CAM-Based Collision Detection VLSI Processor for Robotics (Special Issue on Super Chip for Intelligent Integrated Systems)