スポンサーリンク
Department of computer science and Systems Engineering, Kobe University | 論文
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
- Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
- A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
- A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
- Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications
- A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
- Transceiver Macro with Spread-Spectrum Clocking Capability for AC-Coupled Cable Interfaces
- Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
- A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
- Phase Assignment Algorithm Based on Traffic Measurement for Real-Time MPEG Sources in ATM Networks
- Fluorescence Histochemical Demonstration of Adrenergic Nerve Fibers in the Hip Joint Capsule
- Detection and Evaluation of Security Features Embedded in Paper Using Spectral-Domain Optical Coherence Tomography
- Biomimetic Pinching Movements of a Musculo-Skeletal Dual-Finger Model
- An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter
- A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops