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Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto Univers | 論文
- A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
- A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- ABdis : Approach to Estimating the Distribution of Available Bandwidth for Multimedia QoS Control and Management( Multimedia QoS Evaluation and Management Technologies)
- A Synchronization Method for Synchronous CDMA Broadband Communication Systems with GEO Satellites(Recent Fundamental Technologies for Broadband Satellite Communications)
- Fast and Accurate 3-D Imaging Algorithm with Linear Array Antennas for UWB Pulse Radars
- A Robust and Fast Imaging Algorithm with an Envelope of Circles for UWB Pulse Radars(Sensing)
- A High-Resolution Imaging Algorithm without Derivatives Based on Waveform Estimation for UWB Radars(Sensing)
- An Accurate Imaging Algorithm with Scattered Waveform Estimation for UWB Pulse Radars(Sensing)
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- Optimum Practical Design of Distributed and Asynchronous Power Control for Wireless Networks with Shared Bands(Multi-dimensional Mobile Information Networks)
- Design Tools and Trial Designs for PCA-Chip2
- A 65 nm Complementary Metal--Oxide--Semiconductor 400 ns Measurement Delay Negative-Bias-Temperature-Instability Recovery Sensor with Minimum Assist Circuit
- A Transformation-Based Implementation of Lightweight Nested Functions
- Efficient and Portable Implementation of Java-style Exception Handling in C
- Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
- Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback(VLSI Architecture,VLSI Design and CAD Algorithms)
- An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Design of Realtime 3-D Sound Processing System(Cyberworlds)
- An Imaging Algorithm of a Target with Arbitrary Motion for Ultra Wide-Band Radar with a Small Number of Antennas
- Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation