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Computer School, National University of Defense Technology | 論文
- A hybrid multicast deadlock-free scheme for virtualization at the NoC level
- Self-selection pseudo- circuit: a clever crossbar pre-allocation
- Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
- A novel parallel memory organization supporting multiple access types with matched memory modules
- LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs
- Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
- A cost conscious performance model for media processors
- A novel QPP interleaver for parallel turbo decoder