A cost conscious performance model for media processors

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概要

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• The combination of multi-core, SIMD and VLIW schemes is becoming prevailing in today’s media processor architectures. To achieve a deep insight into this trend, we propose a power conscious performance model based on the rationale of Hill and Marty’s model. Several representative media application kernels are evaluated on the proposed model. The evaluation result shows that: for none communication applications, a large number of small cores achieve optimal performance; for communication applications, architectures with reduced core count and increased core size is preferred. Meanwhile, by increasing the SIMD width, better power efficiency can be achieved for both types of applications at a small loss of performance.

著者

• Chen Shuming

  Computer School, National University of Defense Technology

• Zhang Kai

  Computer School, National University of Defense Technology

• Chen Hu

  Computer School, National University of Defense Technology

• Wang Yaohua

  Computer School, National University of Defense Technology

• Liu Sheng

  Computer School, National University of Defense Technology

• Ning Xi

  Computer School, National University of Defense Technology

• Wan Jianghua

  Computer School, National University of Defense Technology

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• A cost conscious performance model for media processors
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