A novel QPP interleaver for parallel turbo decoder

スポンサーリンク

概要

• 論文の詳細を見る

• Quadratic permutation polynomial (QPP) interleaver is more suitable for parallel turbo decoding due to it is contention-free. However, the parallel address generation of QPP is area-consuming when the parallel degree <I>P</I> is large, and the data shuffle between memory banks and processing elements (PE) introduces large interconnect cost. This paper first evaluates the area and power cost of three typical Parallel Address Generators (PAG) and four typical Data Shuffle Networks (DSN) from academic and industrial area, and then proposes a novel general QPP interleaver with a highly area-efficient PAG and an associated DSN. Our QPP interleaver can support general parallel turbo decoder design. Experimental results show that, for <I>P</I>=64, the area and power cost of the PAG are on average 9.2% and 9.8% of that of the evaluated respectively. Meanwhile, the DSN can also achieve a slight hardware cost reduction, compared with the evaluated works.

著者

• Chen Shuming

  Computer School, National University of Defense Technology

• Zhang Kai

  Computer School, National University of Defense Technology

• Liu Wei

  Computer School, National University of Defense Technology

• Chen Hu

  Computer School, National University of Defense Technology

• Wang Yaohua

  Computer School, National University of Defense Technology

• Liu Sheng

  Computer School, National University of Defense Technology

• Ning Xi

  Computer School, National University of Defense Technology

関連論文

• A novel parallel memory organization supporting multiple access types with matched memory modules
• LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs
• A cost conscious performance model for media processors
• A novel QPP interleaver for parallel turbo decoder

スポンサーリンク