Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA

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概要

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• This paper presents a parameterized multi-standard adaptive radix-4 Viterbi decoder with high throughput and low complexity. The proposed Viterbi decoder supports constraint lengths ranging from 3-9, code rates in the range of 1/2-1/3, and arbitrary truncation lengths. We present a novel fabric of Add-Compare-Select Unit (ACSU) and methods of unsigned quantization and efficient normalization that shorten the critical path. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G. The proposed decoder is implemented on Xilinx XC5VLX330 device and the frequency achieved is 181.7MHz. The throughput of the proposed decoder can reach 363Mbps, which is superior to the other current multi-standard Viterbi decoders or radix-4 Viterbi decoders on the FPGA platform.

著者

• Dou Yong

  Computer School National University Of Defense Technology

• Lei Yuanwu

  Computer School National University Of Defense Technology

• Guo Song

  Computer School National University Of Defense Technology

• NI Shice

  Computer School, National University of Defense Technology

• Ni Shice

  Computer School National University Of Defense Technology

• Li Rongchun

  Computer School National University Of Defense Technology

関連論文

• Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA
• Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA

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