Lee Yeun | Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea
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- Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Koreaの論文著者
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea | 論文
- Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure