Saito Toshihiko | Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation
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概要
Microelectronics Engineering Laboratory, Semiconductor Company, Toshiba Corporation | 論文
- Sub-1.3 nm Amorphous Tantalum Pentoxide Gate Dielectrics for Damascene Metal Gate Transistors
- Sub 1.3nm Amorphous Ta_2O_5 Gate Dielectrics for Damascene Metal Gate Transistor
- Plasma-Damage-Free Gate Process Using Chemical Mechanical Polishing for 0.1 μm MOSFETs
- Plasma Damage Free Gate Process Using CMP for 0.1um MOSFETs
- Effects of Cleavage on Local Cross-Sectional Stress Distribution in Trench Isolation Structure