Miyaji Kousuke | Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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概要
- Miyaji Kousukeの詳細を見る
- 同名の論文著者
- Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japanの論文著者
関連著者
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Takeuchi Ken
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan
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Miyaji Kousuke
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Miyaji Kousuke
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan
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Takeuchi Ken
Department of Electrical Engineering and Information Systems, Chuo University, Bunkyo, Tokyo 112-8551, Japan
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Higuchi Kazuhide
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan
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Higuchi Kazuhide
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Takeuchi Ken
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Johguchi Koh
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Hung Chinglin
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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Shinozuka Yasuhiro
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
著作論文
- Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal--Oxide--Semiconductor Single Transistor Cell
- Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory
- Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme