YOSHINAKA Akira | Semiconductor and Integrated Circuits Division, Hitachi, Ltd.
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概要
Semiconductor and Integrated Circuits Division, Hitachi, Ltd. | 論文
- A 6.93-μm^2 Full CMOS SRAM Cell Technology for 1.8-V High-Performance Cache Memory
- Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells
- Large 1/f Noise in Polysilicon TFT Loads and Its Effects on the Stability of SRAM Cells
- A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits (Special Issue on ULSI Memory Technology)
- Large 1/f Noise in Polysilicon TFT Loads and its Effects on the Stability of SRAM Cells