Chou Tse-Heng | VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
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- VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwanの論文著者
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan | 論文
- Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches
- Improving Boron-Induced Retardation of Metal-Induced Lateral Crystallization Length by Hydrogen Treatment
- Systematic Analysis and Modeling of On-Chip Spiral Inductors for Complementary Metal Oxide Semiconductor Radio Frequency Integrated Circuits Applications
- Hot-Carrier-Induced Degradation on 0.1 μm Partially Depleted Silicon-On-Insulator Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor