Yatsui Takashi | Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan
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- Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japanの論文著者
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo, Bunkyo, Tokyo 113-8656, Japan | 論文
- Endurance Enhancement and High Speed Set/Reset of 50 nm Generation HfO2 Based Resistive Random Access Memory Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme
- Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal--Oxide--Semiconductor Single Transistor Cell
- Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory
- Energy Transfer in Multi-Stacked InAs Quantum Dots