Tang Mao-Chyuan | VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan
スポンサーリンク
概要
- Tang Mao-Chyuanの詳細を見る
- 同名の論文著者
- VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwanの論文著者
VLSI Technology Laboratory, Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan | 論文
- Effect of Etch Stop Layer Stress on Negative Bias Temperature Instability of Deep Submicron p-Type Metal–Oxide–Semiconductor Field Effect Transistors with Dual Gate Oxide
- Extra Bonus on Transistor Optimization with Stress Enhanced Notched-Gate Technology for Sub-90 nm Complementary Metal Oxide Semiconductor Field Effect Transistor
- Investigation and Modeling of Stress Interactions on 90 nm Silicon on Insulator Complementary Metal Oxide Semiconductor by Various Mobility Enhancement Approaches
- Effects of Hot Carriers on DC and RF Performances of Deep Submicron p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Various Oxide Layer Thicknesses