Yamada Keisaku | Waseda University, 513 Waseda Tsurumakicho, Shinjuku, Tokyo 162-0041, Japan

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概要

• Yamada Keisakuの詳細を見る
• 同名の論文著者
• Waseda University, 513 Waseda Tsurumakicho, Shinjuku, Tokyo 162-0041, Japanの論文著者

関連著者

• Miyazaki Seiichi

  Hiroshima Univ.

• Inumiya Seiji

  Semiconductor Company Toshiba Corporation

• YAMADA Keisaku

  Waseda Univ.

• Ohji Yuzuru

  Semiconductor & Integrated Circuits Division Hitachi Ltd.

• Nara Yasuo

  Semiconductor Leading Edge Technologies Inc.

• Sato Motoyuki

  Semiconductor Leading Edge Technologies Inc. (selete)

• Aoyama Takayuki

  Semiconductor Leading Edge Technologies Inc.

• Hasunuma Ryu

  University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-0821, Japan

• Tamura Chihiro

  University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8572, Japan

• Yamabe Kikuo

  University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8572, Japan

• Shiraishi Kenji

  University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-8572, Japan

• Yamada Keisaku

  Waseda University, 513 Waseda Tsurumakicho, Shinjuku, Tokyo 162-0041, Japan

• Yamabe Kikuo

  University of Tsukuba, 1-1-1 Tennodai, Tsukuba, Ibaraki 305-0821, Japan

• Aoyama Takayuki

  Semiconductor Leading Edge Technologies (Selete), Inc., Tsukuba, Ibaraki 305-8569, Japan

• Miyazaki Seiichi

  Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima, Hiroshima 739-8530, Japan

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著作論文

• Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-$k$/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm

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