Yeo Yee-chia | Silicon Nano Device Lab. Department Of Electrical And Computer Engineering National University Of Si
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- 同名の論文著者
- Silicon Nano Device Lab. Department Of Electrical And Computer Engineering National University Of Siの論文著者
Silicon Nano Device Lab. Department Of Electrical And Computer Engineering National University Of Si | 論文
- Silicon Strain-Transfer-Layer (STL) and Graded Source/Drain Stressors for Enhancing the Performance of Silicon-Germanium Channel P-MOSFETs
- N-channel MOSFETs with In-situ Silane-Passivated Gallium Arsenide Channel and CMOS-Compatible Palladium-Germanium Contacts
- Contact Technology employing Nickel-Platinum Germanosilicide Alloys for P-Channel FinFETs with Silicon-Germanium Source and Drain Stressors
- Novel Extended-Pi Shaped Silicon-Germanium (eII-SiGe) Source/Drain Stressors for Strain and Performance Enhancement in P-Channel FinFETs
- Strained N-channel FinFETs with High-stress Nickel Silicide-Carbon Contacts and Integration with FUSI Metal Gate Technology