Hsu Hsin-chyh | Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
スポンサーリンク
概要
- 同名の論文著者
- Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univerの論文著者
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer | 論文
- Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process
- Low-Capacitance and Fast Turn-on SCR for RF ESD Protection
- Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
- Novel Implantation Method to Improve Machine-Model Electrostatic Discharge Robustness of Stacked N-Channel Metal-Oxide Semiconductors (NMOS) in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductors (CMOS) Technology : Semiconductors
- Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications