Onoda H | Kyoto Univ. Kyoto Jpn

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著作論文

Improved Array Architectures of DINOR for 0.5 μm 32 M and 64 Mbit Flash Memories (Special Section on High Speed and High Density Multi Functional LSI Memories)
Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
The Double-Sided Rugged Poly Si (DSR) Technology for High Density DRAMs

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