Chen Jung-sheng | Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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概要
- CHEN Jung-Shengの詳細を見る
- 同名の論文著者
- Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univerの論文著者
関連著者
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Ker Ming‐dou
National Chiao‐tung Univ. Hsinchu Twn
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CHEN Jung-Sheng
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung Univ
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KER Ming-Dou
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung Univ
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Ker Ming-dou
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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Chen Jung-sheng
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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Chu Ching-yun
Silicon Integrated Systems Corp. Science-based Industrial Park
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Ker Ming-dou
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
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Chen Jung-sheng
Nanoelectronics And Gigascale Systems Laboratory Institute Of Electronics National Chiao-tung Univer
著作論文
- Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process
- A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device(Electronic Circuits)