Kanetani Kazuo | Central Research Laboratory Hitachi Ltd.

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Noise Reduction Techniques for a 64kb ECL-CMOS SRAM with a 2ns Cycle Time (Special Issue on LSI Memories)
Redundancy Technique for Ultra-High-Speed Static RAMs
Design of a 2-ns Cycle Time 72-kb ECL-CMOS SRAM Macro
A BiCMOS Circuit Using a Base-Boost Technique for Low-Voltage, Low-Power Application (Special Issue on Low-Power LSI Technologies)
Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM
A 0.65-ns, 72-kb ECL-CMOS RAM Macro for a 1-Mb SRAM(Special Issue on the 1994 VLSI Circuits Symposium)

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