Sekimoto H | Graduate School Of Engineering Tokyo Metropolitan University
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概要
Graduate School Of Engineering Tokyo Metropolitan University | 論文
- Deterministic Built-in Test for Logic Circuits Having Multiple Clocks
- High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model(Special Issue on Test and Verification of VLSI)
- Deterministic Built-in Test with Neighborhood Pattern Generator
- Analytical Model on Hybrid State Saving with a Limited Number of Checkpoints and Bound Rollbacks(Reliability, Maintainability and Safety Analysis)
- Reliability Analysis of a Convolutional-Code-Based Packet Level FEC under Limited Buffer Size(Reliability, Maintainability and Safety Analysis)