Haraguchi Masaru | Renesas Technology
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概要
Renesas Technology | 論文
- A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
- Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
- A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
- Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
- A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector