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Renesas Technology | 論文
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros(Integrated Electronics)
- A Low Power Embedded DRAM Macro for Battery-Operated LSIs(Power Optimization)(VLSI Design and CAD Algorithms)
- Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL(Electronic Circuits)
- A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
- A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
- Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
- A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
- Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
- 招待講演 A 65nm embedded SRAM with wafer level burn-in mode, leak-bit redundancy and E-trim fuse for known good die (集積回路)
- A Design of High-Speed 4-2 Compressor for Fast Multiplier (Special Issue on Ultra-High-Speed LSIs)
- A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test
- A 4500 MIPS/W, 86μA Resume-Standby, 11μA Ultra-Standby Application Processor for 3G Cellular Phones(Digital, Low-Power LSI and Low-Power IP)
- A 286 MHz 64-b Floating Point Multiplier with Enhanced CG Operation
- A 2.6-ns 64-b Fast and Small CMOS Adder (Special Issue on Ultra-High-Speed LSIs)
- An Embedded DRAM Hybrid Macro with Auto Signa Management and Enhanced-on-Chip Tester
- A 0.18 ★m 32 Mb Embedded DRAM Macro for 3-D Graphics Controller
- Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
- A 1.5-V 250-MHz to 3.0-V 622-MHz Operation CMOS Phase-Locked Loop with Precharge Type Phase-Frequency Detector
- A Shared Multibuffer Architecture for High-Speed ATM Switch LSIs (Special Issue on New Architecture LSIs)