NAKATSUKA Shin'ichi | Central Research Lab. Hitachi Ltd.
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概要
Central Research Lab. Hitachi Ltd. | 論文
- A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
- A High-Endurance Read/Write Scheme for Half-V_cc Plate Nonvolatile DRAMs with Ferroelectric Capacitors(Special Issue on Nonvolatile Memories)
- A Robust Array Architecture for a Capacitorless MISS Tunnel-Diode Memory(Integrated Electronics)
- The Advantages of a DRAM-Based Digital Architecture for Low-Power, Large-Scale Neuro-Chips
- An Independent-Source Overdriven Sense Amplifier for Multi-Gigabit DRAM Array