NAKURA Toru | Dept. of Electrical Engineering and Information Systems, The University of Tokyo

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• 同名の論文著者
• Dept. of Electrical Engineering and Information Systems, The University of Tokyoの論文著者

Dept. of Electrical Engineering and Information Systems, The University of Tokyo | 論文

• A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment
• On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch
• On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems
• Simultaneous Localization Assistance for Mobile Robot Navigation in Real, Populated Environments

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