Kwon Sang-Jik | Inter-University Semiconductor Research Center, Seoul National University
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- Inter-University Semiconductor Research Center, Seoul National Universityの論文著者
Inter-University Semiconductor Research Center, Seoul National University | 論文
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Nanoscale Poly-Si Line Formation and Its Uniformity