A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III--V Metal--Oxide--Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8

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概要

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• This paper presents a low damage inductively coupled plasma (ICP) etching process to define sub-100 nm platinum gate lines for III--V metal--oxide--semiconductor field-effect transistors (MOSFETs) fabrication. In this process, a negative resist etching mask patterned by electron beam lithography is used to define the high resolution platinum features using a combination of SF6 and C4F8 etch gases. Systematic investigation of the impact of various etch conditions, such as coil and platen power, gas composition, chamber pressure on etch rate and profile, resulted in a controllable etching process. Optical emission spectra of the ICP plasma have been checked for better understanding the etching mechanism. Etch induced damage of the underlying device channel of the III--V MOSFET materials has been evaluated through monitoring the sheet resistance variation of the materials at room temperature, which showed the process does not significantly degrade the electrical properties of the underlying device channel under optimized conditions.

• 2012-01-25

著者

• Li Xu

  Nanoelectronics Research Centre Department Of Electrical And Electronics Engineering Glasgow Univers

• Zhou Haiping

  Nanoelectronics Research Centre Department Of Electrical And Electronics Engineering Glasgow Univers

• Thayne Iain

  Nanoelectronics Research Centre Department Of Electrical And Electronics Engineering Glasgow University

• Hill Richard

  Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, U.K.

• Holland Martin

  Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, U.K.

• Thayne Iain

  Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, U.K.

• Li Xu

  Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, U.K.

• Zhou Haiping

  Nanoelectronics Research Centre, School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LT, U.K.

関連論文

• Optical Emission Spectrometry of Plasma in Low-Damage Sub-100 nm Tungsten Gate Reactive Ion Etching Process for Compound Semiconductor Transistors
• Low-Hydrogen-Content Silicon Nitride Deposited at Room Temperature by Inductively Coupled Plasma Deposition
• A Low Damage Etching Process of Sub-100 nm Platinum Gate Line for III--V Metal--Oxide--Semiconductor Field-Effect Transistor Fabrication and the Optical Emission Spectrometry of the Inductively Coupled Plasma of SF6/C4F8

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