Bias-Induced Threshold Voltage Shifts in Organic Thin-Film Transistors by Soluble Fullerene Layers on Gate Dielectric

概要

論文の詳細を見る
An investigation of threshold voltage shifts in organic thin-film transistors (TFTs) based on pentacene with an additional soluble fullerene derivatives of [6,6]-phenyl C61-butyric acid methyl ester (PCBM) on gate dielectric. With an additional soluble fullerene layer, the threshold voltage ($V_{\text{th}}$) is optimized from $-3.9$ to $-1.1$ V without affect the mode operation of the devices, while retaining the carrier mobility (0.02--0.03 cm2 V-1 s-1) and on/off current ratio (${\sim}10^{4}$). Furthermore, the existence of PCBM agglomerates as electron acceptor-like traps resulted in a shift of $V_{\text{th}}$ in the positive and reversible directions depending on the magnitude of gate bias ($V_{\text{bias}}$) as well as duration of time bias ($T_{\text{bias}}$). The device operation changed into normally-on (depletion--accumulation) mode upon positive $V_{\text{bias}}$ as the duration of $T_{\text{bias}}$ was increased, which attributes to the formation of a conductive layer at the pentacene--fullerene interface. Moreover, the recovery of $V_{\text{th}}$ was further enhanced by a high negative $V_{\text{bias}}$ for a short duration. In addition, the mobility was minimally affected by both $V_{\text{bias}}$ conditions.
2011-01-25