Investigation of Spacer Engineering on n-Type Field Effect Transistor Performance during Laser Spike Annealing
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概要
- 論文の詳細を見る
A new liner oxide spacer structure of n-type field effect transistors (n-FETs) with a favorable stress optimum has been investigated to improve the crystallization in the amorphous area of the source–drain extension (SDE) implantation during laser spike annealing. The dopant activation performance of n+ polycrystalline silicon is identical to the sheet resistance judgement for two spacer schemes of n-FETs devices, but the junction leakage of the oxide liner spacer is lower than that of the conventional composite spacer. The stress within SDE depth induced by the spacer is changed from compressive to tensile stress when the conventional composite spacer was replaced by the oxide liner spacer.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2010-06-25
著者
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Lee Sanboh
Department Of Materials Science And Engineering National Tsing Hua University
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Chen Hao-Yu
National Nano Device Laboratories, Hsinchu 300, Taiwan
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Hao-Yu Chen
National Nano Device Laboratories, Hsinchu 300, Taiwan
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Huang Chien-Chao
Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 300, Taiwan
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Sanboh Lee
Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 300, Taiwan
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Chien-Chao Huang
Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu 300, Taiwan
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