Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

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概要

• 論文の詳細を見る

• As the design rule of integrated circuits is shrinking rapidly, it is necessary to use low-$k_{1}$ lithography technologies. With low-$k_{1}$ lithography, even if aggressive optical proximity correction is adopted, many sites become marginless spots, known as “hotspots”. For this problem, hotspot fixer (HSF) in design-for-manufacturability flow has been studied. In our previous work, we indicated the feasibility of layout modification using a simple line/space sizing rule for metal layers in 65-nm-node logic devices. However, in view of the continuous design-rule shrinkage and design complication, a more flexible modification method has become necessary to fix various types of hotspots. In this work, we have developed a brute-force model-based HSF. To further reduce the processing time, the hybrid flow of rule- and model-based HSFs is studied. The feasibility of such hybrid flow is studied by applying it to the full-chip layout modification of a logic test chip.

• 2010-06-25

著者

• KOBAYASHI Sachiko

  Advanced LSI Technology Laboratory, Toshiba Corporation

• Suigen Kyoh

  Advanced Lithography Process Technology Department, Device Process Development Center, Corporate Research & Development Center, Toshiba Corporation, Yokohama 235-8522, Japan

• Soichi Inoue

  Advanced Lithography Process Technology Department, Device Process Development Center, Corporate Research & Development Center, Toshiba Corporation, Yokohama 235-8522, Japan

• Kyoh Suigen

  Advanced Lithography Process Technology Department, Device Process Development Center, Corporate Research & Development Center, Toshiba Corporation, Yokohama 235-8522, Japan

• Kotani Toshiya

  Advanced Lithography Process Technology Department, Device Process Development Center, Corporate Research & Development Center, Toshiba Corporation, Yokohama 235-8522, Japan

• Yoko Takekawa

  Advanced Lithography Process Technology Department, Device Process Development Center, Corporate Research & Development Center, Toshiba Corporation, Yokohama 235-8522, Japan

• Koji Nakamae

  Department of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University, Suita, Osaka 565-0871, Japan

関連論文

• Highly Accurate Process Proximity Correction Based on Empirical Model for 0.18 μm Generation and Beyond
• Development of An Accurate Optical Proximity Correction System for 1 Gbit Dynamic Random Access Memory Fabrication
• Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

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