Hot-Carrier Degradation in Low-Temperature Polycrystalline Silicon n-Channel Lightly Doped Drain Thin-Film Transistors
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概要
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The hot-carrier degradation mechanism in low-temperature polycrystalline silicon (poly-Si) n-channel lightly doped drain (LDD) thin-film transistors (TFTs) is investigated. The degradation is characterized by transconductance degradation ($\Delta G_{\text{m}}$) at low drain voltage ($V_{\text{d}}$) and decreases in substrate current ($I_{\text{sub}}$) and kink current at high $V_{\text{d}}$. It is assumed that the trapped negative charges (acceptor-type trap states) in the gate edge region, mostly outside and partly inside the gate, contribute to hot-carrier degradation after stress under current saturation bias. The degradation presumably first occurs outside the gate in the LDD region and, with increasing stress time, the electron-trapped region expands toward the channel under the gate owing to the saturation of electrons in the trap states. At high-$V_{\text{d}}$ bias, a decrease in the lateral electric field in the gate-edge region due to the presence of negative charges reduces $I_{\text{sub}}$ and the drain current $I_{\text{d}}$, thereby reducing the kink current. At low-$V_{\text{d}}$ bias, the current flow near the upper interface in the gate-edge region decreases after the stress owing to the generated negative charges. The negative charges lead to the decrease in $I_{\text{d}}$ in the deep-gate voltage $V_{\text{g}}$ region in $V_{\text{g}}$–$I_{\text{d}}$ characteristics.
- 2009-01-25
著者
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Tango Hiroyuki
Department Of Image Engineering Tokyo Polytechnic University
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Satoh Toshifumi
Department Of Image Engineering Tokyo Polytechnic University
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Yamagata Masahiro
Department of Image Engineering, Tokyo Polytechnic University, 1583 Iiyama, Atsugi, Kanagawa 243-0297, Japan
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Hirata Seishiro
Department of Image Engineering, Tokyo Polytechnic University, 1583 Iiyama, Atsugi, Kanagawa 243-0297, Japan
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