Electrical Conduction in 10 nm Thin Polysilicon Wires from 4 to 400 K and Their Operation for Hybrid Memory

概要

論文の詳細を見る
This paper reports on the experimental investigation of conduction mechanisms in gated ultra-thin polysilicon nanowires (polySiNW) over a wide range of temperature: from 4 to 400 K. Some irregular Coulomb oscillations (CO) are observed at temperatures lower than 200 K showing several periods due to the random mixture of grain sizes (5–20 nm). We report increased oscillations at intermediate range of temperatures (between 50 and 150 K) and at high drain voltages in polySiNW with a mixture of grain sizes. Monte Carlo (MC) simulations performed on an array of conductive islands connected to each other by tunnel junctions (modeling the nanograin polysilicon) validate the experimental observations and a first order theory is proposed. Finally, the V-shape (ambipolar) drain current versus gate voltage ($I_{\text{DS}}$–$V_{\text{GS}}$) characteristic and related hysteresis of the polySiNW is exploited for building a novel hybrid polySiNW-NMOS memory circuit cell.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2006-06-30