Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

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概要

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• In this study, the gate-to-drift overlap length of lateral double diffused metal–oxide–semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 μm complementary metal–oxide–semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 μm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 μm showed the longest on-resistance hot-carrier lifetime of $9.34 \times 10^{5}$ s, along with a breakdown voltage of 22 V and an on-resistance of 23 m$\Omega$$\cdot$mm2.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2006-03-15

著者

• Ha Jong-Bong

  Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea

• Choi Moon-Ho

  Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea

• Kim Nam-Soo

  Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea

• Na Kee-Yeol

  Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea

• Kim Yeong-Seuk

  Dept. of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk 361-763, Korea

関連論文

• Silicon Complementary Metal–Oxide–Semiconductor Field-Effect Transistors with Dual Work Function Gate
• Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal–Oxide–Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

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