Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide
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概要
- 論文の詳細を見る
In this paper the novel robust Hemispherical Grain (HSG)-merged Al2O3/HfO2 (AHO) capacitor with diagonal cell array scheme and double mold oxide (DMO) is introduced. The capacitor process with diagonal cell array scheme and double mold oxide can maximize storage node (SN) height up to 2.0 μm in 0.11 μm dynamic random access memory (DRAM) technology by enlarging the bottom size of SN. Also we developed the HSG-merged AHO capacitor for the first time in mass production. The HSG-merged AHO capacitor technique exhibited a capacitance enhancement by 24% without any significant decrease in breakdown voltage compared to Al2O3 (ALO) capacitor.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-04-15
著者
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Moon Hong-joon
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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KIM Sun-Joon
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd.
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HONG Hyeong-Sun
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd.
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Cho Tai-heui
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Lee Kang-yoon
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Lee Si-woo
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Lee Sung-hyun
Fab 3 Team Memory Division Samsung Electronics Co. Ltd.
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Kang Hyuck-jin
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Kim Hyun-chul
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Kim Seong-goo
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Oh Kyung-seok
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Park Don
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Jeon Sang-kil
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Jeong Sang-moo
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Suk Jong-gyu
Fab 3 Team Memory Division Samsung Electronics Co. Ltd.
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Hyun Chang-suk
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Jung Jae-hwang
Dram Process Architecture Team Memory Division Samsung Electronics Co. Ltd.
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Jeon Young-soo
Fab 3 Team Memory Division Samsung Electronics Co. Ltd.
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Jeon Sang-Kil
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Jeon Young-Soo
Fab 3 Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Lee Si-Woo
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Kim Sun-Joon
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Kim Hyun-Chul
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Moon Hong-Joon
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Oh Kyung-Seok
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Hong Hyeong-Sun
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Suk Jong-Gyu
Fab 3 Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Kim Seong-Goo
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Jeong Sang-Moo
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Kang Hyuck-Jin
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Lee Kang-Yoon
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Cho Tai-Heui
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
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Park Don
DRAM Process Architecture Team, Memory Division, Samsung Electronics Co., Ltd., San #16, Banwol-Ri, Taean-Eup, Hwasung-City, Gyeonggi-Do 445-701, Korea
関連論文
- Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide
- Robust Metal/AHO/HSG-Cylinder Capacitor Technology Using Diagonal Cell Array Scheme and Double Mold Oxide