Fully Depleted SOI Complementary MOS Device with Raised Source/Drain for 90 nm Embedded Static RAM Technology

概要

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Fully depleted silicon-on-insulator (FD SOI) devices with 70 nm gate lengths for embedded static random access memory (SRAM) technology were investigated for different SOI film thickness. Transistor performances of 700 μA/μm and 320 μA/μm were obtained for n-type and p-type metal-oxide semiconductor field effect transistor (NMOSFET and PMOSFET) devices, respectively at 1.0 V operation voltage and $I_{\text{off}}=75$ nA/μm. Si selective epitaxial growth (SEG) process was well optimized. Both the single raised (SR) and double raised (DR) source/drain process were studied to reduce parasitic series resistance. For the DR process, both NMOSFET and PMOSFET performance are improved by 9 and 13% respectively, compared to the SR process. Drain induced barrier lowering (DIBL) was improved from 100 mV to 13 mV as the SOI film thickness was scaled down from 50 nm to 17 nm. Due to the self-heating effect, the AC current is 15% higher than the DC current for the case of 40 nm SOI thickness. The static noise margin (SNM) for a 1.1 μm2 6T-SRAM cell was 210 mV and ring oscillator speed was improved by 24% compared to bulk devices.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2004-04-15