Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

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概要

• 論文の詳細を見る

• High-$k$ insulators are currently considered for SiO2 replacement as gate dielectrics in sub-100 nm complementary metal-oxide-semiconductor (CMOS) technology nodes. The use of double-layer high-$k$ stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the programming speed. In this paper, the influence of the high-$k$ parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low-$k$/high-$k$ dielectric stacks and confirm the theoretical results based on our experimental data.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2003-04-15

著者

• Van Houdt

  Imec Leuven Spdt Division

• Govoreanu Bogdan

  IMEC Leuven, SPDT Division, Kapeldreef 75, B-3001 Leuven, Belgium

• Blomme Pieter

  IMEC Leuven, SPDT Division, Kapeldreef 75, B-3001 Leuven, Belgium

• De Meyer

  IMEC Leuven, SPDT Division, Kapeldreef 75, B-3001 Leuven, Belgium

関連論文

• Time Dependent Anomalous Charge Loss Modeling in Flash Memories and an Accelerated Testing Procedure
• Performance of Direct Tunneling Floating Gate Memory with Medium-$\kappa$ Dielectrics for Embedded-Random-Access Memory Applications
• Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

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