An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System
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概要
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An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 8×8 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39dB for a 1.11kHz analog input signal at a sampling rate of 100kS/s. The power consumption and core area are 38.71µW and 0.059mm2, respectively.
著者
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Jang Young-chan
Analog Integrated Circuit Lab. School Of Electronic Engineering Kumoh National Instisute Of Technology
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Eo Ji-hun
Analog Integrated Circuit Lab. School Of Electronic Engineering Kumoh National Instisute Of Technology
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JEONG Yeon-Ho
Analog Integrate Circuit Lab., Kumoh National Institute of Technology, Gumi
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- An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System
- An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System