Hamming network circuits based on CMOS/memristor hybrid design
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概要
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Memristor, as an innovative technology, has been proposed in the application of neural networks since its physical implementation was reported by HP lab. In this paper, we proposed a Hamming network circuits based on CMOS/memristor hybrid design which is compact in device size and circuit structure. Through HSPICE simulation, pattern recognition and classification functions of hamming network circuits are demonstrated using a 16×16 nanocrossbar memory.
著者
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Yi Xun
State Key Laboratory of High Performance Computing, National University of Defense Technology
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Zhu Xuan
State Key Laboratory of High Performance Computing, National University of Defense Technology
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Yang Xuejun
State Key Laboratory of High Performance Computing, National University of Defense Technology
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Wu Chunqing
School of Computer, National University of Defense Technology
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Wu Junjie
State Key Laboratory of High Performance Computing, National University of Defense Technology
関連論文
- Hamming network circuits based on CMOS/memristor hybrid design
- VACED-SIM: A Simulator for Scalability Prediction in Large-Scale Parallel Computing
- Multi-level programming of memristor in nanocrossbar