A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer

スポンサーリンク

概要

• 論文の詳細を見る

• We explore a dual-band fractional-N PLL synthesizer with 3.5mW, 5µsec settling time and 15µsec start-up time in 0.18µm CMOS technology. The power consumption is minimized through the design efforts in LC-VCO design to maximize the quality factor of an integrated inductor up to 6.1 at 866MHz and minimize the VCO gain by a capacitor tuning technique with an on-chip nonvolatile memory and the proper choice of varactor. Measured results of a prototype fractional-N PLL satisfy the required settling and start-up times, and indicate that the phase noises at 10kHz and 100KHz offset are -108.7dBc/Hz and -98.3dBc/Hz, respectively, and the reference spurious level is -81.6dBc.

著者

• Lee Jun

  Research Institute Of Electrical Communication Tohoku University

• Masui Shoichi

  Research Institute Of Electrical Communication Tohoku University

関連論文

• C-12-48 Optimization of Program and Restore Operations in CMOS-Compatible Nonvolatile Latch
• C-12-59 3.5mW 15μsec-Start-Up 5μsec-Settling Fractional-N PLL Synthesizer
• A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer
• A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

スポンサーリンク