C-12-59 3.5mW 15μsec-Start-Up 5μsec-Settling Fractional-N PLL Synthesizer

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概要

• 論文の詳細を見る
• 2012-03-06

著者

• Lee Jun

  Research Institute Of Electrical Communication Tohoku University

• Masui Shoichi

  Research Institute Of Electrical Communication Tohoku University

• Masui Shoichi

  Research Institute of Electrical Communication, Tohoku University

関連論文

• C-12-48 Optimization of Program and Restore Operations in CMOS-Compatible Nonvolatile Latch
• C-12-59 3.5mW 15μsec-Start-Up 5μsec-Settling Fractional-N PLL Synthesizer
• A 3.5mW 5µsec settling time dual-band fractional-N PLL synthesizer
• A 32-bit 16-program-cycle nonvolatile memory for analog circuit calibration in a standard 0.18µm CMOS

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