Cluster mesh: a topology for three-dimensional network-on-chip

スポンサーリンク

概要

• 論文の詳細を見る

• Three-dimensional network-on-chip (3D NoC) is a promising method to overcome the bottlenecks in 3D integrated circuit (IC). Although 3D NoC can provide more efficient inter-layer communication with through-silicon vias (TSVs), the low yield and high overhead become the main challenges. To obtain a balance point between cost and performance, the cluster mesh we proposed applies a new vertical interconnects squeezing scheme which decreases the amount of TSV by sharing vertical links through vertical routers. The simulation results show that the proposed topology can improve the yield of chip, reduce the overhead and provide acceptable performance.

著者

• Gu Huaxi

  State Key Lab Of Isn Xidian University

• Wang Junhui

  State Key Laboratory of ISN, Xidian University

• Yang Yintang

  Institute of Microelectronics, Xidian University

関連論文

• Routing in Hexagonal Networks under a Corner-Based Addressing Scheme(Networks)
• Cluster mesh: a topology for three-dimensional network-on-chip
• A multi-wavelength communication strategy for 2D-mesh Network-on-Chip
• Thermal and competition aware mapping for 3D network-on-chip
• Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip
• RONoC: A Reconfigurable Architecture for Application-Specific Optical Network-on-Chip
• A Bufferless Optical Network-on-Chip Router
• Energy- and Traffic-Balance-Aware Mapping Algorithm for Network-on-Chip

スポンサーリンク