Soft-Error on Memory ICs Induced by D-T Neutrons.
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概要
- 論文の詳細を見る
<BR>In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of CMOS SRAM ICs were irradiated around room temperature with 14 MeV neutrons from OKTAVIAN. The pattern and rate of soft-error upsets on the ICs were measured in situ during neutron irradiation. It was found that neutron reactions caused not multiple but single type soft-errors and the number of the soft-errors increased proportionally with neutron fluence. There was also a large difference in the soft-error upset rate between set (from 0 to 1) and reset (from 1 to 0) soft-errors for some kinds of ICs. Considering the cell population in a chip, we obtained the neutron susceptibility constant, i.e. bit soft-error cross section of 23 × 10-15 cm2 for 16 K and 64 K bit CMOS SRAM ICs, and 69 × 10-14 cm2 for 256 K and 1 Mbit ICs, respectively. Also, all memory cells were controllable after neutron irradiation and no permanent damage was caused by neutron fluence irradiation below about 1012 n/cm2.
- 一般社団法人 日本原子力学会の論文
著者
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Miyazaki Hiroaki
Department Of Molecular Cell Physiology Graduate School Of Medical Science Kyoto Prefectural Univers
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Iida Toshiyuki
Department Of Electronic Information Systems And Energy Engineering Guraduate School Of Osaka Univer
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Takahashi Akito
Department Of Nuclear Engineering Graduate School Of Engineering Osaka University
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MIYAZAKI Hiroaki
Department of Nuclear Engineering, Faculty of Engineering, Osaka University
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DATEMICHI Jun
Department of Nuclear Engineering, Faculty of Engineering, Osaka University
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HO KK
Department of Nuclear Engineering, Faculty of Engineering, Osaka University
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