Multiple-Valued Constant-Power Adder and Its Application to Cryptographic Processor
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概要
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This paper proposes a constant-power adder based on multiple-valued logic and its application to cryptographic processors being resistant to side-channel attacks. The proposed adder is implemented in Multiple-Valued Current-Mode Logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of input values, which makes it possible to prevent power-analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we focus on a multiple-valued Binary Carry-Save adder based on the Positive-Digit (PD) number system and its application to RSA processors. The power characteristic of the proposed design is evaluated with HSPICE simulation using 90nm process technology. The result shows that the proposed design can achieve constant power consumption with lower performance overhead in comparison with the conventional binary design.
著者
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HOMMA Naofumi
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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AOKI Takafumi
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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BABA Yuichi
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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MIYAMOTO Atsushi
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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