A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique

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概要

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• A 7bit 1.0Gsps Cascaded Folding ADC is presented. This ADC employs cascaded folding architecture with 3-degree folders. A new reset technique and layout shuffling enable the ADC to operate at high-speed with low power consumption. Implemented in a 90nm CMOS process technology the ADC consumes 230mW with 1.2V and 2.5V supplies and has a SNR of 38dB.

著者

• ONO Koichi

  Sony Corporation

• OHKAWA Takeshi

  Sony Corporation

• SEGAMI Masahiro

  Sony Corporation

• HOTTA Masao

  Tokyo City University

関連論文

• A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
• A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique
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