Hardware implementation of a tessellation accelerator for the OpenVG standard
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概要
- 論文の詳細を見る
The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.
著者
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Kim Seung
School of Advanced Materials Engineering, Chonbuk National University, Chonju-si, Chonbuk 561-756, Korea
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Ro Won
School of Electrical and Electronic Engineering, Yonsei University
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Oh Yunho
School of Electrical and Electronic Engineering, Yonsei University
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Park Karam
School of Electrical and Electronic Engineering, Yonsei University
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Kim Seung
School of Electrical and Electronic Engineering, Yonsei University
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- Hardware implementation of a tessellation accelerator for the OpenVG standard
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