Delay Testing: Improving Test Quality and Avoiding Over-testing
スポンサーリンク
概要
- 論文の詳細を見る
Delay testing is one of key processes in production test to ensure high quality and high reliability for logic circuits. Test escape missing defective chips can be reduced by introducing delay testing. On the other hand, we need to concern yield loss caused by delay testing, i.e., over-testing. Many methods and techniques have been developed to solve problems on delay testing. In this paper, we introduce fundamental techniques of delay testing and survey recent problems and solutions. Especially we focus on techniques to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.
- 一般社団法人情報処理学会の論文
- 2011-08-10
著者
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Tomokazu Yoneda
Nara Institute of Science and Technology | JST, CREST
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Seiji Kajihara
Kyushu Institute of Technology
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Seiji Kajihara
Kyushu Institute of Technology | JST, CREST
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Satoshi Ohtake
Nara Institute of Science and Technology | JST, CREST
関連論文
- Estimation of Delay Test Quality and Its Application to Test Generation
- On Delay Test Quality for Test Cubes
- Delay Testing: Improving Test Quality and Avoiding Over-testing