20303 3次元実装用シリコン貫通電極形成のための銅めっき技術(OS3 機械工学が支援する微細加工技術(半導体・MEMS・NEMS)(1),オーガナイズドセッション)

概要

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A copper electroplating process of via filling for three-dimensional packaging was investigated using electrochemical analysis and computational fluid dynamics (CFD) simulation. A new plating solution was selected and applied to a dip-type plating system with paddle agitation. The plating solution has suppression function of Cu deposition that depends upon flow rate of the solution. The paddle agitation in the vertical dip-type plating cell was used for making a conformed agitation flow over wafer. The flow in via and over wafer surface caused by the reciprocating paddles was simulated using CFD. The results suggest that it is important to adjust the right paddle speed for each via size. This optimal combination of the plating solution and the plating system with paddle agitation achieves the bottom-up filling for Through Silicon Via (TSV) without void formation.
一般社団法人日本機械学会の論文
2010-03-09